IBM? has promised its partners that its Power 6 processors will hit between 4 to 5GHz pretty soon now,(current Power5 clocked at 2.3 Ghz) speed with each SMT2 core accessing 4MB of L2 memory, and sitting astirde a 32MB level three controller.
Power6, a dual-core chip IBM will begin manufacturing this year for servers going on sale in mid-2007, is the latest in a series of server processors that are central to Big Blue's recovery in the Unix server market. In terms of revenue, IBM reached the top spot in the market in 2005 over Hewlett-Packard and Sun Microsystems, though the company has given back some of those gains in the first half of 2006.
The Power family, which also includes lower-end PowerPC models, competes chiefly with Itanium chips from Intel, Sparc from Sun and Fujitsu, and x86 chips from Intel and Advanced Micro Devices.
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A Power 6 can thrust data of 64B/two cycles to Data Level One cache, with an aggregate L2 bandwidth of 127B/5 cycles per core. Data from the SMP fabric onto the chip will achieve 67 per cent times 40B/two cycles at peak.
A dual core chip will have nine execution units per core, with 790 million transistors on a 341 square millimetre die, with seven way superscalar performance and two memory controllers per chip, while it will be built on SOI 65 nanometre CMOS.
Big Glue will offer a whole series of alternate Power 6 bins, swapping cache depending on what customers want to build into their systems.
IBM claims that its 65 nanometer technology will offer a 30 per cent performance improvement over 90 nanometre chips, and use a a high performance SRAM cell.
The Power 6 core will have nine execution units, and reduces logic stages per cycle to 13FO4s to give higher frequencies.
IBM also has moved some higher-end reliability features from its mainframe line to Power6. The idea is to catch and fix as many errors as possible before software has to be interrupted.
